Silicon carbide semiconductor device

ABSTRACT

In an edge termination region, first to third electric field mitigating layers are provided in a concentric shape surrounding an active region. Between adjacent first to third electric field mitigating layers, p-type first to third space-modulated regions are provided each of which is closer to a chip edge than is the third electric field mitigating layer. Each of the space-modulated regions is formed by, from an inner side, a low-concentration sub-region and a high-concentration sub-region arranged to alternately repeat in a concentric shape surrounding the electric field mitigating layer on the inner side. Preferable, lengths (Lb1, Lb2, Lb3) of the first to third space-modulated regions are set to satisfy Lb1≤Lb2&lt;Lb3 and preferably lengths (La1, La2, La3) of the first to third electric field mitigating layers are set to satisfy La1&lt;La2&lt;La3. A rate of increase of the lengths of the first to third electric field mitigating layers may be constant.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation application of International ApplicationPCT/JP2017/021394 filed on Jun. 8, 2017, which claims priority from aJapanese Patent Application No. 2016-140795 filed on Jul. 15, 2016, thecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

Embodiments of the invention relate to a silicon carbide semiconductordevice.

2. Description of the Related Art

In semiconductor devices (hereinafter, silicon carbide semiconductordevices) using a silicon carbide (SiC) semiconductor material, formationof a breakdown voltage structure for obtaining stable high breakdownvoltages has been demanded. As such a breakdown voltage structure, ajunction termination extension (JTE) structure is known that is formedby arranging in an edge termination region, a p⁻-type low-concentrationregion having an impurity concentration lower than that of a p-typehigh-concentration region that forms a pn junction with an n⁻-type driftlayer. The p⁻-type low-concentration region is arranged adjacently to anouter side (side toward a chip edge) of the p-type high-concentrationregion. The edge termination region is a region that surrounds aperiphery of an active region. The edge termination region mitigateselectric field in the active region toward a chip front surface andsustains the breakdown voltage. The active region is a region throughwhich current flows in an ON state.

The JTE structure is constituted by plural p⁻-type low-concentrationregions (hereinafter, electric field mitigating regions) arrangedadjacently in a concentric shape surrounding the periphery of the activeregion, and the closer a p⁻-type low-concentration region is arranged tothe chip edge, the lower is an impurity concentration of the p⁻-typelow-concentration region. Points of electric field concentration atouter edges of the electric field mitigating regions constituting theJTE structure are distributed, whereby maximum electric field strengthis reduced. As for conventional JTE structures, a structure has beenproposed that includes a region (hereinafter, space-modulated region) inwhich between adjacent electric field mitigating regions, a p-typesub-region having an impurity concentration equal to that of aninner-side electric field mitigating layer and a p-type sub-regionhaving an impurity concentration equal to that of an outer-side electricfield mitigating layer are arranged to be adjacent and alternatelyrepeat in a concentric shape surrounding the periphery of the activeregion (for example, refer to Japanese Patent No. 5554415 (paragraphs0049, 0065, FIGS. 9, 11)).

A conventional breakdown voltage structure will be described. FIG. 10 isa cross-sectional view of an example of a conventional breakdown voltagestructure. FIG. 10 corresponds to FIG. 11 in Japanese Patent No.5554415. The left-hand side of FIG. 10 depicts regions closer toward anactive region and the right-hand side depicts regions closer toward achip edge (similarly in FIG. 11). The conventional breakdown voltagestructure depicted in FIG. 10 is constituted by three electric fieldmitigating layers (p⁻-type region, p⁻⁻-type region, and p⁻⁻⁻-typeregion) 111, 112, 113 and three space-modulated regions 121, 122, 123,where the closer an electric field mitigating layer 111, 112, 113 isarranged to the chip edge of a silicon carbide base (semiconductor chip)104, the lower is an impurity concentration of the electric fieldmitigating layer 111, 112, 113. The silicon carbide base 104 is formedby forming by epitaxial growth on a front surface of an n⁺-typesemiconductor substrate (hereinafter, n⁺-type silicon carbide substrate:not depicted) containing silicon carbide, an n⁻-type silicon carbidelayer constituting an n⁻-type drift layer 102.

At a boundary of the active region and the edge termination region 110,a p-type guard ring 103 is selectively provided in a surface layer on afront surface (surface on the n⁻-type drift layer 102 side) of thesilicon carbide base 104. The p-type guard ring 103 surrounds aperiphery of the active region. In the edge termination region 110, thefirst, second, third electric field mitigating layers 111, 112, 113 inorder stated from nearest the active region toward the chip edge areselectively provided in the surface layer on the front surface of thesilicon carbide base 104, closer to the chip edge than is the p-typeguard ring 103. The first, second, third electric field mitigatinglayers 111, 112, 113 are arranged in a concentric shape surrounding aperiphery of the p-type guard ring 103. The first electric fieldmitigating layer 111 is in contact with the p-type guard ring 103. Thefirst, second, third electric field mitigating layers 111, 112, 113 eachhave a uniform impurity concentration distribution.

Between the adjacent first, second, third electric field mitigatinglayers 111, 112, 113, the first and second space-modulated regions 121,122 are provided, respectively. The third space-modulated region 123 isprovided closer to the chip edge than is the third electric fieldmitigating layer 113, and is in contact with the third electric fieldmitigating layer 113. The first, second, third space-modulated regions121, 122, 123 are in contact with the electric field mitigating layers111, 112, 113 adjacent thereto. The first, second, third space-modulatedregions 121, 122, 123 are constituted by p-type regions (hereinafter,high-concentration sub-regions) 131 having an impurity concentrationsubstantially equal to the impurity concentration of the electric fieldmitigating layer 111, 112, 113 adjacent thereto on an inner side (sidetoward the active region) thereof, and p-type regions (hereinafter,low-concentration sub-regions) 132 having an impurity concentrationsubstantially equal to the impurity concentration of the electric fieldmitigating layer 111, 112, 113 adjacent thereto on an outer side (sidetoward the chip edge) thereof (in the third space-modulated region 123,the low-concentration sub-regions 132 have an impurity concentrationsubstantially equal to that of the n⁻-type drift layer 102).

The low-concentration sub-regions 132 and the high-concentrationsub-regions 131 are arranged to be adjacent and alternately repeattoward the chip edge, in a concentric shape surrounding a periphery ofthe electric field mitigating layer 111, 112, 113 adjacent thereto onthe inner side thereof. In the space-modulated regions 121, 122, 123,the closer a high-concentration sub-region 131 is arranged to the chipedge, the narrower is a width (width in a direction from the inner sidethereof toward the chip edge) x₁₀₁ thereof; and the closer alow-concentration sub-region 132 is arranged to the chip edge, the wideris a width (width in the direction from the inner side thereof towardthe chip edge) x₁₀₂ thereof. A depletion layer that spreads from theactive region, passes through regions constituting these breakdownvoltage structures and spreads through the edge termination region 110toward the chip edge. As a result, electric field in the silicon carbidebase 104 becomes uniform and is mitigated, whereby the breakdown voltageis ensured. In particular, the first, second, high electric field isuniformly retained by the third space-modulated regions 121, 122, 123,enabling high breakdown voltage to be ensured.

As another breakdown voltage structure, a structure having optimizedconditions for the space-modulated regions has been proposed. One set ofa high-concentration sub-region and a low-concentration sub-region isregarded as one equal-concentration region and in one space-modulatedregion, the closer the equal-concentration region is arranged to thechip edge, the lower is an equal-concentration (average impurityconcentration) thereof. A reduction rate of a ratio between theequal-concentrations of adjacent equal-concentration regions isconstant. The space-modulated region is divided into plural sectionsthat each includes one or more adjacent equal-concentration regions,where an average impurity concentration difference between adjacentsections is equal (for example, refer to International Publication No.WO 2016/103814 (paragraphs 0121 to 0127, FIG. 20)). In InternationalPublication No. WO 2016/103814, electric field concentration atboundaries of the high-concentration sub-regions and thelow-concentration sub-regions is mitigated, electric field distributionin the space-modulated region is further equalized, and the breakdownvoltage is further improved.

An example of this conventional breakdown voltage structure will bedescribed. FIG. 11 is a cross-sectional view of an example of theconventional breakdown voltage structure. FIG. 11 corresponds to FIG. 20in International Publication No. WO 2016/103814. In the conventionalbreakdown voltage structure depicted in FIG. 11, a space-modulatedregion (here, indicated as a first space-modulated region 121) isdivided into plural sections (here, 4) 141, 142, 143, 144 that eachincludes one or more adjacent equal-concentration regions 130 (sub-areasincluding one set of the high-concentration sub-region 131 and thelow-concentration sub-region 132). Additionally, the closer a section141 to 144 is arranged to the chip edge, the narrower is a width x₁₀₁ ofthe high-concentration sub-region 131 therein. Other than the width x₁₀of the high-concentration sub-region 131 in the sections 141 to 144,configuration of the conventional breakdown voltage structure depictedin FIG. 11 is similar to the conventional breakdown voltage structurethat depicted in FIG. 10.

Further, in the silicon carbide semiconductor device, to obtain stablehigh breakdown voltages, reduction of the maximum electric fieldstrength in a gel that seals a semiconductor chip in a package (resincase) has been disclosed (for example, refer to Japanese Patent No.5600698 (paragraphs 0005, 0021, FIG. 3)). In Japanese Patent No.5600698, a surface protecting film formed on an electric fieldmitigating region in an edge termination region has a 2-layer structureincluding an inorganic layer and a resin layer, where a thickness of theresin layer, a dielectric constant difference of the inorganic layer andthe resin layer, etc. are optimized, thereby reducing the maximumelectric field strength in a sealant.

SUMMARY OF THE INVENTION

According to an embodiment of the invention, a silicon carbidesemiconductor device includes a semiconductor substrate of a firstconductivity type containing silicon carbide; an active region providedat a front surface of the semiconductor substrate and through which amain current flows; a plurality of second-conductivity-typesemiconductor regions selectively provided in a concentric shapesurrounding a periphery of the active region, the plurality ofsecond-conductivity-type semiconductor regions having differing impurityconcentrations that are relatively lower with increasing proximity ofrespective ones of the plurality of second-conductivity-typesemiconductor regions to a chip edge; a plurality of first intermediateregions of a second conductivity type, each first intermediate region ofthe plurality of first intermediate regions being provided between andin contact with adjacent second-conductivity-type semiconductor regionsof the plurality of second-conductivity-type semiconductor regions, andeach first intermediate region having an impurity concentration that islower than an impurity concentration of an adjacentsecond-conductivity-type semiconductor region on an inner side and thatis higher than an impurity concentration of another adjacentsecond-conductivity-type semiconductor region on an outer side; and asecond intermediate region of the second conductivity type providedcloser to the chip edge than is an outermost second-conductivity-typesemiconductor region that is nearest the chip edge among the pluralityof second-conductivity-type semiconductor regions, the secondintermediate region being in contact with the outermostsecond-conductivity-type semiconductor region and having an impurityconcentration that is lower than the impurity concentration of theadjacent second-conductivity-type semiconductor region on an inner sideand that is higher than an impurity concentration of the semiconductorsubstrate. The plurality of first intermediate regions and the secondintermediate region are each formed by, from the inner side, a firstsub-region of the second conductivity type and a second sub-region ofthe second conductivity type arranged to be adjacent and to alternatelyrepeat in a concentric shape surrounding a periphery of the adjacentsecond-conductivity-type semiconductor region on the inner side, thesecond sub-region having an impurity concentration that is higher thanan impurity concentration of the first sub-region. The secondintermediate region has a length that is longer than respective lengthsof the plurality of first intermediate regions.

In the embodiment, each first intermediate region of the plurality offirst intermediate regions has a length that is at least equal to alength of an adjacent first intermediate region on the inner sidethereof.

In the embodiment, each second-conductivity-type semiconductor region ofthe plurality of second-conductivity-type semiconductor regions has alength that is longer than a length of the adjacentsecond-conductivity-type semiconductor region on the inner side thereof.

In the embodiment, differences in respective lengths of adjacentsecond-conductivity-type semiconductor regions are all equal.

In the embodiment, the impurity concentration of the first sub-region ofrespective first intermediate regions of the plurality of firstintermediate regions is equal to the impurity concentration of therespective another adjacent second-conductivity-type semiconductorregion on the outer side.

In the embodiment, the impurity concentration of the first sub-region ofthe second intermediate region is equal to the impurity concentration ofthe semiconductor substrate.

In the embodiment, the impurity concentration of the second sub-regionis equal to the impurity concentration of the adjacentsecond-conductivity-type semiconductor region on the inner side.

In the embodiment, the silicon carbide semiconductor device furtherincludes a surface protecting film provided on a front surface of thesemiconductor substrate, the surface protecting film covering theplurality of second-conductivity-type semiconductor regions, theplurality of first intermediate regions and the second intermediateregion. The surface protecting film has a thickness that is at least amaximum thickness that is formable by a single session of an applicationprocess, based on viscosity of a material used in forming the surfaceprotecting film.

According to another embodiment, a silicon carbide semiconductor deviceincludes a semiconductor substrate of a first conductivity type andcontaining silicon carbide; an active region provided at a front surfaceof the semiconductor substrate and through which a main current flows; aplurality of second-conductivity-type semiconductor regions selectivelyprovided in a concentric shape surrounding a periphery of the activeregion, the plurality of second-conductivity-type semiconductor regionshaving differing impurity concentrations that are relatively lower withincreasing proximity of respective ones of the plurality ofsecond-conductivity-type semiconductor regions to a chip edge; aplurality of first intermediate regions of a second conductivity type,each first intermediate region of the plurality of first intermediateregions being provided between and in contact with adjacentsecond-conductivity-type semiconductor regions of the plurality ofsecond-conductivity-type semiconductor regions, and each firstintermediate region having an impurity concentration that is lower thanan impurity concentration of an adjacent second-conductivity-typesemiconductor region on an inner side and that is higher than animpurity concentration of another adjacent second-conductivity-typesemiconductor region on an outer side; and a second intermediate regionof the second conductivity type provided closer to the chip edge than isan outermost second-conductivity-type semiconductor region that isnearest the chip edge among the plurality of second-conductivity-typesemiconductor regions, the second intermediate region being in contactwith the outermost second-conductivity-type semiconductor region andhaving an impurity concentration that is lower than the impurityconcentration of the adjacent second-conductivity-type semiconductorregion on an inner side and that is higher than an impurityconcentration of the semiconductor substrate. The plurality of firstintermediate regions and the second intermediate region are each formedby, from the inner side, a first sub-region of the second conductivitytype and a second sub-region of the second conductivity type arranged tobe adjacent and to alternately repeat in a concentric shape surroundinga periphery of the adjacent second-conductivity-type semiconductorregion on the inner side, the second sub-region having an impurityconcentration that is higher than an impurity concentration of the firstsub-region. The plurality of second-conductivity-type semiconductorregions each has a length that is longer than a length of the adjacentsecond-conductivity-type semiconductor region on the inner side.

In the embodiment, the silicon carbide semiconductor device furtherincludes a surface protecting film provided on the front surface of thesemiconductor substrate, the surface protecting film covering theplurality of second-conductivity-type semiconductor regions, theplurality of first intermediate regions and the second intermediateregion. The surface protecting film has a thickness that is at least amaximum thickness that is formable by a single session of an applicationprocess, based on viscosity of a material used in forming the surfaceprotecting film.

Objects, features, and advantages of the present invention arespecifically set forth in or will become apparent from the followingdetailed description of the invention when read in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram depicting a breakdown voltage structure of asemiconductor device according to an embodiment;

FIG. 1B is a diagram depicting the breakdown voltage structure of thesemiconductor device according to the embodiment;

FIG. 2 is an enlarged cross-sectional view of a single space-modulatedregion depicted in FIG. 1B;

FIG. 3 is an enlarged cross-sectional view of the breakdown voltagestructure in FIG. 1B;

FIG. 4 is an enlarged cross-sectional view of another example of thebreakdown voltage structure depicted in FIG. 1B;

FIG. 5 is a characteristics diagram depicting electric field strengthdistribution at a surface of a surface protecting film in first andsecond examples;

FIG. 6 is a characteristics diagram depicting electric field strengthdistribution in a silicon carbide base of the first and second examples;

FIG. 7 is a characteristics diagram depicting electric field strengthdistribution at a surface of a surface protecting film in third andfourth examples;

FIG. 8 is a characteristics diagram depicting electric field strengthdistribution in a silicon carbide base of third and fourth examples;

FIG. 9 is characteristics diagram depicting electric field strengthdistribution at a surface of a surface protecting film in a fifthexample;

FIG. 10 is a cross-sectional view of an example of a conventionalbreakdown voltage structure; and

FIG. 11 is a cross-sectional view of an example of the conventionalbreakdown voltage structure.

DETAILED DESCRIPTION OF THE INVENTION

First, problems associated with the related arts will be described. Ingeneral, a semiconductor chip is mounted in a module package and sealedby, for example, a gel, with a front surface of the semiconductor chipbeing covered by a surface protecting film such as a polyimide film.Here, when a semiconductor chip (hereinafter, Si chip) containingsilicon (Si) is used, a length (hereinafter, edge length) of the edgetermination region is long, whereby electric field in Si chip toward thefront surface is mitigated, local electrical discharge due to electricfield concentration, etc. does not occur. The edge length is a lengthfrom a boundary the active region and the edge termination region 110 tothe chip edge.

Nonetheless, when a semiconductor chip (hereinafter, SiC chip)containing silicon carbide is used, application of the conventionalbreakdown voltage structures (refer to FIGS. 10, 11) enables the edgelength to be reduced. However, problem arises in that electric fieldstrength on a front surface (surface of the surface protecting film) ofthe SiC chip increases. Therefore, at the surface of the surfaceprotecting film (not depicted) in the SiC chip alone or at an interfaceof the gel and the surface protecting film when the SiC chip is sealedby the gel or the like, electrical discharge occurs and dielectricbreakdown may occur at the surface protecting film on the front surfaceof the SiC chip, rather than inside the SiC chip.

As a measure to circumvent this problem, the edge length of the SiC chipmay be increased to be about equal to the edge length of the Si chip.However, as described above, with the SiC chip, a predeterminedbreakdown voltage may be obtained at a shorter edge length as comparedto the Si chip. Therefore, increasing the edge length of the SiC chip tobe about equal to the edge length of the Si chip to obtain thepredetermined breakdown voltage increases the amount of chip area thatis useless. Therefore, from the perspective of breakdown voltage, a newproblem arises in that the size of the SiC chip increases.

Embodiments of a silicon carbide semiconductor device according to thepresent invention will be described in detail with reference to theaccompanying drawings. In the present description and accompanyingdrawings, layers and regions prefixed with n or p mean that majoritycarriers are electrons or holes. Additionally, + or − appended to n or pmeans that the impurity concentration is higher or lower, respectively,than layers and regions without + or −. In the description of theembodiments below and the accompanying drawings, main portions that areidentical will be given the same reference numerals and will not berepeatedly described.

A structure of the silicon carbide semiconductor device according to anembodiment will be described. FIGS. 1A and 1B are diagrams depicting abreakdown voltage structure of a semiconductor device according to theembodiment. FIG. 1A depicts a planar layout and FIG. 1B depicts across-sectional view of the structure along cutting line A-A′ in FIG.1A. In FIGS. 1A and 1B, to clearly show an overall layout of thebreakdown voltage structure, regions constituting the breakdown voltagestructure are not depicted. The planar layout is a planar shape and anarrangement configuration of constituent regions as viewed from a frontsurface of a silicon carbide base 4. FIG. 2 is an enlargedcross-sectional view of a single space-modulated region depicted in FIG.1B. FIG. 3 is an enlarged cross-sectional view of a breakdown voltagestructure in FIG. 1B.

As depicted in FIG. 1, the semiconductor device according to theembodiment includes a silicon carbide base (semiconductor chip(semiconductor substrate)) 4 having an active region 10 a and an edgetermination region 10 b. The silicon carbide base 4 epitaxial substrateformed by forming epitaxial growth on a front surface of an n⁺-typesemiconductor substrate (n⁺-type silicon carbide substrate) 1 containingsilicon carbide (SiC), an n⁻-type silicon carbide layer 2 constitutingan n⁻-type drift layer. The active region 10 a is a region through whichcurrent flows in the ON state. The edge termination region 10 b is aregion that surrounds a periphery of the active region 10 a, andmitigates electric field toward a chip front surface in the activeregion 10 a.

In the active region 10 a, a predetermined element structure (notdepicted) is provided such as a Schottky barrier diode (SBD), a metaloxide semiconductor field effect transistor (MOSFET), an insulated gatebipolar transistor (IGBT), etc. Reference numerals 5, 6 are respectivelya front electrode and a rear electrode constituting the predeterminedelement structure.

In the active region 10 a, on a front surface of the silicon carbidebase 4, the front electrode 5 is provided and is in contact with then⁻-type silicon carbide layer 2. The front electrode 5 is further incontact with a p-type guard ring 3 described hereinafter. The frontelectrode 5 may extend onto a field oxide film 7 described hereinafter.On a rear surface of the silicon carbide base 4, the rear electrode 6 isprovided spanning from the active region 10 a, across the edgetermination region 10 b. The field oxide film 7 covers the front surfaceof the silicon carbide base 4 in the edge termination region 10 b. Athickness t1 of the field oxide film 7 may be in a range from 0.3 μm to1.0 μm. On the front electrode 5 and the field oxide film 7, a surfaceprotecting film 8 (refer to FIG. 3) such as a polyimide film isprovided.

The field oxide film 7 covers a later described JTE structure of theedge termination region 10 b and electrically insulates the JTEstructure and the front electrode 5. An end of the field oxide film 7toward the active region 10 a may extend onto the p-type guard ring 3.In FIG. 1, for example, a SBD is depicted. In this case, the frontelectrode 5 is an anode electrode and the rear electrode 6 is a cathodeelectrode. The front electrode 5 is provided on the front surface of thesilicon carbide base 4, forms a Schottky junction with the n⁻-type driftlayer (n⁻-type silicon carbide layer 2), and is in contact with thep-type guard ring 3. The p-type guard ring 3 surrounds a periphery ofthe Schottky junction between the n⁻-type drift layer and the frontelectrode 5.

At a boundary of the active region 10 a and the edge termination region10 b, in a surface layer on the front surface of the silicon carbidebase 4, the p-type guard ring 3 is selectively provided so as tosurround the periphery of the active region 10 a. The p-type guard ring3 is provided spanning from the active region 10 a into the edgetermination region 10 b. Further, in the edge termination region 10 b,first, second, third electric field mitigating layers(second-conductivity-type semiconductor regions: a p⁻-type region, ap⁻⁻⁻-type region, and a p⁻⁻⁻-type region) 11, 12, 13 sequentially inorder from nearest the active region 10 a toward a chip edge (edge ofthe semiconductor chip) are each selectively provided in the surfacelayer on the front surface of the silicon carbide base 4, closer to thechip edge than is the p-type guard ring 3.

The first, second, third electric field mitigating layers 11, 12, 13 arearranged in a concentric shape surrounding a periphery of the p-typeguard ring 3. The first electric field mitigating layer 11 is in contactwith the p-type guard ring 3. An impurity concentration of the firstelectric field mitigating layer 11 is lower than an impurityconcentration of the p-type guard ring 3. The closer the first, second,third electric field mitigating layer 11, 12, 13 is arranged to the chipedge, the lower is an impurity concentration of the first, second, thirdelectric field mitigating layer 11, 12, 13. The first, second, thirdelectric field mitigating layers 11, 12, 13 have a similar (uniform)impurity concentration distribution in a direction from the activeregion 10 a toward the chip edge and in a depth direction. Lengths(lengths in a direction from the active region 10 a toward the chipedge) La1, La2, La3 of the first, second, third electric fieldmitigating layers 11, 12, 13 will be described hereinafter (refer toFIG. 3).

Between the first, second, third electric field mitigating layers 11,12, 13 that are adjacent and at a position closer to the chip edge thanis the third electric field mitigating layer 13, a space-modulatedregion (a first to third respectively assigned reference numerals 21,22, 23 sequentially from nearest the active region 10 a toward the chipedge) are provided. The first space-modulated region (first intermediateregion) 21 is provided between the first electric field mitigating layer11 and the second electric field mitigating layer 12, and is in contactwith the first and second electric field mitigating layers 11, 12. Thesecond space-modulated region (first intermediate region) 22 is providedbetween the second electric field mitigating layer 12 and the thirdelectric field mitigating layer 13, and is in contact with the secondand third electric field mitigating layers 12, 13. The thirdspace-modulated region (second intermediate region) 23 is providedcloser to the chip edge than is the third electric field mitigatinglayer 13 and is in contact with the third electric field mitigatinglayer 13.

Respective impurity concentrations of the first, second, thirdspace-modulated regions 21, 22, 23 are lower than an impurityconcentration of the electric field mitigating layer 11, 12, 13 adjacentthereto on an inner side (side toward the active region 10 a) thereof;and are higher than the impurity concentration of the electric fieldmitigating layer 11, 12, 13 adjacent thereto on an outer side (sidetoward the chip edge) thereof (the impurity concentration of the thirdspace-modulated region 23 is higher than an impurity concentration ofthe type silicon carbide layer 2). The lengths (lengths in the directionfrom the active region 10 a toward the chip edge) La1, La2, La3 of thefirst, second, third space-modulated regions 21, 22, 23 will bedescribed hereinafter (refer to FIG. 3). Depths of the first, second,third electric field mitigating layers 11, 12, 13 and of the first,second, third space-modulated regions 21, 22, 23 may be equal, and maybe variously adjusted so as to satisfy the above impurity concentrationdifference between adjacent regions. The first, second, third electricfield mitigating layers 11, 12, 13 and the first, second, thirdspace-modulated regions 21, 22, 23 constitute the breakdown voltagestructure (JTE structure).

As depicted in FIG. 2, the first, second, third space-modulated regions21, 22, 23 are each constituted by p-type regions (hereinafter,high-concentration sub-regions (second sub-regions)) 31 having animpurity concentration substantially equal to the impurity concentrationof the electric field mitigating layer 11, 12, 13 adjacent thereto onthe inner side thereof, and p-type regions (hereinafter,low-concentration sub-regions (first sub-regions)) 32 having an impurityconcentration substantially equal to the impurity concentration of theelectric field mitigating layer 11, 12, 13 adjacent thereto on the outerside thereof (the impurity concentration of the third space-modulatedregion 23 is substantially equal to the impurity concentration of then⁻-type silicon carbide layer 2). The left-hand side of FIG. 2 depictsregions closer toward the active region 10 a (inner side) and theright-hand side of FIG. 2 depicts regions closer toward the chip edge(outer side) (similarly in FIGS. 3 and 4). FIG. 2 depicts the firstspace-modulated region 21. Further, in FIG. 2, the field oxide film 7and the surface protecting film 8 are not depicted.

The high-concentration sub-regions 31 and the low-concentrationsub-regions 32 are arranged to be adjacent and alternately repeat towardthe chip edge, in a concentric shape surrounding a periphery of theelectric field mitigating layer 11, 12, 13 adjacent thereto on the innerside thereof. In particular, at an innermost side (side nearest theactive region 10 a) of the space-modulated region 21, 22, 23, thelow-concentration sub-region 32 is arranged so as to be in contact withthe electric field mitigating layer 11, 12, 13 on the inner side of thespace-modulated region 21, 22, 23 (for example, in the case of the firstspace-modulated region 21, the first electric field mitigating layer11); and at an outermost side (side nearest the chip edge) of thespace-modulated region 21, 22, 23, the high-concentration sub-region 31is provided so as to be in contact with the electric field mitigatinglayer 21, 22, 23 on the outer side of the space-modulated region 21, 22,23 (for example, in the case of the first space-modulated region 21, thesecond electric field mitigating layer 12). In the third space-modulatedregion 23, similarly to the conventional breakdown voltage structure(refer to FIG. 10), in place of the low-concentration sub-region 32, then⁻-type silicon carbide layer 2 is arranged.

In a single set of a high-concentration sub-region 31 and an adjacentlow-concentration sub-region 32, a width (width in a direction from theinner side toward the chip edge) and the impurity concentration of thehigh-concentration sub-region 31 are assumed to be x₁ and n_(p1),respectively, while a width (width in the direction from the inner sidetoward the chip edge) and the impurity concentration of thelow-concentration sub-region 32 are assumed to be x₂ and n_(p2),respectively. In this case, in the space-modulated region 21, 22, 23, anaverage impurity concentration N_(p) of a single equal-concentrationregion 30 that includes a single set of the high-concentrationsub-region 31 and the adjacent low-concentration sub-region 32 isexpressed by equation (1). Further, the space-modulated region 21, 22,23 may be assumed to be constituted by plural equal-concentrationregions 30 arranged adjacently in a direction from the inner side of thespace-modulated region 21, 22, 23 toward the chip edge.N _(p)=((x ₁ ×n _(p1))+(x ₂ ×n _(p2)))/(x ₁ +x ₂)  (1)

The widths x₁, x₂ of the high-concentration sub-region 31 and thelow-concentration sub-region 32 may be variously changed and based onthe widths x₁, x₂, the average impurity concentration N_(p) of theequal-concentration regions 30 is set, whereby an impurity concentrationdistribution of the space-modulated region 21, 22, 23, in the directionfrom the inner side thereof toward the chip edge may be variouslychanged. For example, the impurity concentration distribution of thespace-modulated region 21, 22, 23 may approach an impurity concentrationdistribution substantially equivalent to an impurity concentrationdistribution that gradually decreases from the inner side of thespace-modulated region 21, 22, 23 toward the chip edge. In FIG. 2,regions (the first electric field mitigating layer 11 and thehigh-concentration sub-region 31, the second electric field mitigatinglayer 12 and the low-concentration sub-region 32) having substantiallyequal impurity concentrations are indicated by similar hatchingpatterns.

An average impurity concentration per unit area of the first, second,third space-modulated regions 21, 22, 23, for example, is anintermediate impurity concentration between the electric fieldmitigating layer 11, 12, 13 adjacent thereto on the inner side thereof,and the electric field mitigating layer 11, 12, 13 adjacent thereto onthe outer side thereof (for the third space-modulated region 23, then⁻-type silicon carbide layer 2 adjacent thereto on the outer sidethereof). Further, provided the impurity concentration condition aboveand conditions of the lengths Lb1, Lb2, Lb3 of the first, second, thirdspace-modulated regions 21, 22, 23 are satisfied, the first, second,third space-modulated regions 21, 22, 23 may be variously changed suchas in the widths x₁, x₂ of the high-concentration sub-region 31 and thelow-concentration sub-region 32, the number of alternating repetitionsof the high-concentration sub-region 31 and the low-concentrationsub-region 32 (hereinafter, repeating pitch count), etc. according todesign conditions.

The widths x₁, x₂ the high-concentration sub-region 31 and thelow-concentration sub-region 32, for example, may be similar to widthsin the conventional breakdown voltage structures depicted in FIGS. 10and 11 (hereinafter, simply, the conventional breakdown voltagestructure). In particular, for example, the closer thehigh-concentration sub-region 31 is arranged to the chip edge, thenarrower is the width x₁; and the closer the low-concentrationsub-region 32 is arranged to the chip edge, the wider is the width x₂.Further, a single set of a high-concentration sub-region 31 and anadjacent low-concentration sub-region 32 is assumed to be a singleequal-concentration region and in a single space-modulated region 21,22, 23, the closer the equal-concentration region is arranged to thechip edge, the lower is the equal-concentration (average impurityconcentration) thereof. In addition, a reduction rate of a ratio betweenthe equal-concentrations of adjacent equal-concentration regions may beconstant; the space-modulated region 21, 22, 23 may be divided intoplural sections that each includes one or more adjacentequal-concentration regions; and the average impurity concentrationdifference between adjacent sections may be equal.

The lengths La1, La2, La3 of the first, second, third electric fieldmitigating layers 11, 12, 13, and lengths Lb1, Lb2, Lb3 of the first,second, third space-modulated regions 21, 22, 23 will be described withreference to FIG. 3. A length (edge length) of the edge terminationregion 10 b is set to be a shortest length that enables the breakdownvoltage, which is determined by the maximum electric field strength in asilicon carbide part (in the silicon carbide base 4), to be ensured at apredetermined breakdown voltage, and is about equal to the edge lengthin the conventional breakdown voltage structure. The edge length is alength from the boundary of the active region 10 a and the edgetermination region 10 b to the chip edge. The lengths La1, La2, La3 ofthe first, second, third electric field mitigating layers 11, 12, 13,and the lengths Lb1, Lb2, Lb3 of the first, second, thirdspace-modulated regions 21, 22, 23 are determined according to the edgelength. The closer the first, second, third electric field mitigatinglayers 11, 12, 13 are arranged to the chip edge, the longer the lengthsLa1, La2, La3 may be (refer to expression (2)).La1<La2<La3  (2)

The length Lb3 of the third space-modulated region 23 is longer than thelengths Lb1, Lb2 of the first and second space-modulated regions 21, 22.The closer the first, second, third space-modulated regions 21, 22, 23are arranged to the chip edge, the longer the lengths Lb1, Lb2, Lb3 maybe (refer to expression (3)). The lengths Lb1, Lb2 of the first andsecond space-modulated regions 21, 22 may be equal (refer to expression(4)). The lengths Lb1, Lb2, Lb3 of the first, second, thirdspace-modulated regions 21, 22, 23 are longer than the lengths La1, La2,La3 of the first, second, third electric field mitigating layers 11, 12,13 (La1<La2<La3<Lb1 and, expression (3) or expression (4)). For example,the length La3 of the third electric field mitigating layer 13 may beabout ⅙ to 1/10 of the length L3 of the third space-modulated region 23.Lb1<Lb2<Lb3  (3)Lb1≤Lb2<Lb3  (4)

By forming the breakdown voltage structure to satisfy at leastexpression (2) or expression (4), electric field applied to the surfaceprotecting film 8 on the front surface of the silicon carbide base 4 maybe made uniform, while the electric field strength in the siliconcarbide base 4 is set to be about equal to that in the conventionalbreakdown voltage structure and the breakdown voltage is maintained. Asa result, the electric field strength at the surface of the surfaceprotecting film 8 in the SiC chip (the silicon carbide base 4) alone, orat the interface of the gel and the surface protecting film 8 when theSiC chip is sealed by the gel or the like may be reduced (refer to FIGS.5 and 6 described hereinafter). Therefore, breakdown voltage and an edgelength about equal to those in the conventional breakdown voltagestructure are maintained, and the occurrence of electrical discharge atthe surface of the surface protecting film 8 and/or at the interface ofthe surface protecting film 8 and the gel may be suppressed.

For example, the edge length is a length that is 10 to 11 times aminimum required thickness of the n⁻-type drift layer, based on thedevice breakdown voltage. Further, the length La3 of the third electricfield mitigating layer 13 is about 40% of the edge length. Although notparticularly limited hereto, for example, when the semiconductor deviceaccording to the embodiment has a breakdown voltage of 1700V, the edgelength is about 180 μm; the length La3 of the third electric fieldmitigating layer 13 is about 5 μm; and the length L3 of the thirdspace-modulated region 23 is about 45 μm. When the semiconductor deviceaccording to the embodiment has a breakdown voltage of 3300V, the edgelength is about 310 μm; the length La3 of the third electric fieldmitigating layer 13 is about 7 μm; and the length L3 of the thirdspace-modulated region 23 is about 90 μm. In this manner, with increasesin the breakdown voltage, the length of the edge termination region 10 bis increased and a ratio of the length L3 of the third space-modulatedregion 23 with respect to the length of the edge termination region 10 bis increased.

In configuring the breakdown voltage structure of the embodiment, forexample, the respective lengths La1, La2, La3, Lb1, Lb2, Lb3 of thefirst, second, third electric field mitigating layers 11, 12, 13 and thefirst, second, third space-modulated regions 21, 22, 23 are set to atleast satisfy expression (2) or expression (4). Increases and decreasesof the widths x₁, x₂ of the high-concentration sub-region 31 and thelow-concentration sub-region 32 are the same for the first, second,third space-modulated regions 21, 22, 23; and the repeating pitch countof the high-concentration sub-region 31 and the low-concentrationsub-region 32 is set so that the respective lengths Lb1, Lb2, Lb3thereof are satisfied. Therefore, the breakdown voltage structure of theembodiment may be formed by merely changing, at a formation process ofthe conventional breakdown voltage structure, the patterning of ionimplantation masks for forming the high-concentration sub-regions 31 andthe low-concentration sub-regions 32 of the first, second, thirdspace-modulated regions 21, 22, 23 and the first, second, third electricfield mitigating layers 11, 12, 13.

FIG. 4 is an enlarged cross-sectional view of another example of thebreakdown voltage structure depicted in FIG. 1B. As depicted in FIG. 4,the first, second, third electric field mitigating layers 11, 12, 13satisfy expression (2) and with increasing proximity to the chip edge,the lengths La1, La2, La3 may be increased by a constant rate α (referto equation (5)). In other words, differences (=rates α of increase) ofthe lengths La1, La2, La3 between adjacent first, second, third electricfield mitigating layers 11, 12, 13 are equal. By satisfying equation(5), the electric field strength at the surface of the surfaceprotecting film 8 in the SiC chip (the silicon carbide base 4) alone, orat the interface of the gel and the surface protecting film 8 when theSiC chip is sealed by the gel or the like may be reduced (refer to FIGS.7 and 8 described hereinafter).La2=La1+α, and La3=La1+2·α=La2+α  (5)

Further, within the predetermined edge length, at least expression (2)or expression (4) is satisfied, and the lengths La1, La2, La3 of thefirst, second, third electric field mitigating layers 11, 12, 13 may beas short as possible while the lengths Lb1, Lb2, Lb3 of the first,second, third space-modulated regions 21, 22, 23 may be as long aspossible. A reason for this is that by increasing the lengths Lb1, Lb2,Lb3 of the first, second, third space-modulated regions 21, 22, 23, theeffect of reducing the electric field strength at the surface of thesurface protecting film 8 may be enhanced as compared to increasing thelengths La1, La2, La3 of the first, second, third electric fieldmitigating layers 11, 12, 13.

Further, the thicker a thickness t2 of the surface protecting film 8 is,the greater is a distance from the surface of the surface protectingfilm 8 or from the interface of the surface protecting film 8 and thegel to the front electrode 5 and therefore, the electric field strengthat the surface protecting film 8 may be further suppressed, and theelectrical discharge at the surface of the surface protecting film 8, orthe interface of the surface protecting film 8 and the gel may befurther suppressed. For example, normally, the thickness t2 of thesurface protecting film 8 is set to be a thickness that may reliablyprevent an intrusion of water from outside the semiconductor device, thethickness t2 being set based on a maximum thickness (for example, about10 μm) that may be realized by a single session of an applicationprocess, depending on a viscosity of a material such as, for example,polyimide used in forming the surface protecting film 8. Therefore, forexample, the thickness t2 of the surface protecting film 8 may be madeup to a thickness (about 20 μm) that is two times the maximum thicknessof a single session of the application process by performing theapplication process twice using the same material.

A method of manufacturing the semiconductor device according to theembodiment will be described with reference to FIGS. 1 to 3. First, then⁺-type silicon carbide substrate (semiconductor wafer) 1 constitutingthe n⁺-type cathode layer is prepared. Next, on the front surface of then⁺-type silicon carbide substrate 1, the n⁻-type silicon carbide layer 2constituting the n⁻-type drift layer is formed by epitaxial growth,whereby an epitaxial wafer (the silicon carbide base 4) is fabricated.Next, by photolithography and ion implantation of a p-type impurity, atthe boundary of the active region 10 a and the edge termination region10 b, the p-type guard ring 3 is selectively formed in the surface layeron the front surface of the silicon carbide base 4.

Next, on the front surface of the silicon carbide base 4, an ionimplantation mask having openings for a formation region of the firstelectric field mitigating layer 11 and formation regions of thehigh-concentration sub-regions 31 of the first space-modulated region 21is formed, for example, using a resist material or a silicon dioxidefilm (SiO₂). Next, a p-type impurity is ion implanted using the ionimplantation mask as a mask, whereby in the surface layer on the frontsurface of the silicon carbide base 4, the first electric fieldmitigating layer 11 and the high-concentration sub-regions 31 of thefirst space-modulated region 21 are each formed. At this time, otherregions constituting the breakdown voltage structure are covered by theion implantation mask and therefore, the p-type impurity is notimplanted therein.

Next, the ion implantation mask is selectively removed, exposingformation regions of the second electric field mitigating layer 12, thelow-concentration sub-regions 32 of the first space-modulated region 21,and the high-concentration sub-regions 31 of the second space-modulatedregion 22. Next, a p-type impurity is ion implanted using the ionimplantation mask as a mask, whereby in the surface layer on the frontsurface of the silicon carbide base 4, the second electric fieldmitigating layer 12, the low-concentration sub-regions 32 of the firstspace-modulated region 21, and the high-concentration sub-regions 31 ofthe second space-modulated region 22 are each selectively formed.Further, in this ion implantation, impurity concentrations of otherregions exposed in the openings of the ion implantation mask areincreased.

Next, the ion implantation mask is selectively removed, exposingformation regions of the third electric field mitigating layer 13, thelow-concentration sub-regions 32 of the second space-modulated region22, and the high-concentration sub-regions 31 of the thirdspace-modulated region 23. Next, a p-type impurity is ion implantedusing the ion implantation mask as a mask, whereby in the surface layeron the front surface of the silicon carbide base 4, the third electricfield mitigating layer 13, the low-concentration sub-regions 32 of thesecond space-modulated region 22, and the high-concentration sub-regions31 of the third space-modulated region 23 are each selectively formed.Further, in this ion implantation, impurity concentrations of otherregions exposed in the openings of the ion implantation mask areincreased.

In this manner, in the first, second, third electric field mitigatinglayers 11, 12, 13, and the high-concentration sub-regions 31 and thelow-concentration sub-regions 32 of the first, second, thirdspace-modulated regions 21, 22, 23, regions having equal impurityconcentrations are concurrently exposed in sequence and ion implantationof a p-type impurity is performed. In the third space-modulated region23, the low-concentration sub-regions 32 are formed by the n⁻-typesilicon carbide layer 2 and therefore, the third space-modulated region23 may be formed by forming only the high-concentration sub-regions 31.Thus the first, second, third electric field mitigating layers 11, 12,13 and the first, second, third space-modulated regions 21, 22, 23 maybe formed by ion implantations (three ion implantations) for forming thefirst, second, third electric field mitigating layers 11, 12, 13.Subsequently, the ion implantation mask is removed.

The first, second, third electric field mitigating layers 11, 12, 13,and the high-concentration sub-regions 31 and the low-concentrationsub-regions 32 of the first, second, third space-modulated regions 21,22, 23 may be formed in ascending order of impurity concentration. Inthis case, ion implantation for forming regions (i.e., the thirdelectric field mitigating layer 13, the high-concentration sub-regions31 of the third space-modulated region 23) having the lowest impurityconcentration is performed in all formation regions of the first,second, third electric field mitigating layers 11, 12, 13, and thehigh-concentration sub-regions 31 and the low-concentration sub-regions32 of the first, second, third space-modulated regions 21, 22, 23.Subsequent ion implantations are sequentially performed by covering withan ion implantation mask, regions previously formed and having animpurity concentration lower than the regions that are to be formed.

After formation of the breakdown voltage structure, remaining processes(for example, formation of the field oxide film 7, the surfaceprotecting film 8, the front electrode 5, and the rear electrode 6) areperformed. Thereafter, the semiconductor wafer is cut (diced) intoindividual chips, whereby the SBD depicted in FIGS. 1 to 3 is completed.

The electric field strength in the silicon carbide base 4 and at a frontsurface (opposite a rear surface of the surface protecting film 8 facingthe silicon carbide base 4) of the surface protecting film 8 in the edgetermination region 10 b was verified. FIG. 5 is a characteristicsdiagram depicting electric field strength distribution at a surface of asurface protecting film in first and second examples. FIG. 6 is acharacteristics diagram depicting electric field strength distributionin a silicon carbide base of the first and second examples. FIG. 7 is acharacteristics diagram depicting electric field strength distributionat a surface of a surface protecting film in third and fourth examples.FIG. 8 is a characteristics diagram depicting electric field strengthdistribution in a silicon carbide base of third and fourth examples.FIGS. 5 and 6 further depict electric field strength distribution at asurface of a surface protecting film in a conventional example. FIGS. 7and 8 further depict electric field strength distribution in a siliconcarbide base of a conventional example.

The first, second, third, and fourth examples include the breakdownvoltage structure constituted by the first, second, third electric fieldmitigating layers 11, 12, 13, and the first, second, thirdspace-modulated regions 21, 22, 23. In addition, the first examplesatisfies the conditions of only expression (2). The second examplesatisfies the conditions of only expression (4). The third examplesatisfies the conditions of expression (2) and expression (4). Thefourth example satisfies the conditions of expression (5) and expression(4). The conventional example includes the conventional breakdownvoltage structure depicted in FIG. 11 described above, and satisfiesnone of the conditions of expressions (2) to (5). Although not depicted,in the conventional breakdown voltage structure depicted in FIG. 10described above, the electric field strength was confirmed by theinventor to be higher than that of the conventional breakdown voltagestructure depicted in FIG. 11. In the first to fourth examples and inthe conventional example, configuration was similar excluding therespective lengths of the first, second, and third electric fieldmitigating layers and the respective lengths of the first, second, andthird space-modulated regions. The edge length in the first to fourthexamples and in the conventional example was 170 μm.

For the first and second examples, results of measurement of theelectric field strength at the surface of the surface protecting film 8and in the silicon carbide base 4 are depicted in FIGS. 5 and 6,respectively. For the third and fourth examples, results of measurementof the electric field strength at the surface of the surface protectingfilm 8 and in the silicon carbide base 4 are depicted in FIGS. 7 and 8,respectively. For the conventional example, the same results ofmeasurement of the electric field strength at the surface of the surfaceprotecting film are depicted in FIGS. 5 and 7 and the same results ofmeasurement of the electric field strength in the silicon carbide baseare depicted in FIGS. 6 and 8. In FIGS. 5 to 8, a horizontal axis is adistance [μm] in a direction from the boundary of the active region 10 aand the edge termination region 10 b (distance=0 μm) toward the chipedge and a vertical axis is the electric field strength [arbitrary unit(a.u.)] (similarly in FIG. 9).

From the results depicted in FIGS. 5 and 7, in the first to fourthexamples and in the conventional example, the electric field strength atthe surface of the surface protecting film was confirmed to be higherwith increasing distance from the boundary of the active region 10 a andthe edge termination region 10 b toward the chip edge. Further, from theresults depicted in FIG. 5, it was confirmed that in the first andsecond examples, electric field strength at the surface of the surfaceprotecting film 8 at a position 41 indicating the maximum electric fieldstrength could be reduced for the conventional example, and it wasconfirmed that the electric field strength at the surface of the surfaceprotecting film 8 could be made more uniform than in the conventionalexample. In other words, in the conventional example, by satisfying theconditions of expression (2) or expression (4), the electric field thatconcentrates at the position 41 indicating the maximum electric fieldstrength may be distributed to be applied to the surface protecting film8 overall.

Further, from the results depicted in FIG. 7, it was found that in acase of a breakdown voltage structure that similar to the third example,satisfies the conditions of both expression (2) and expression (4),results similar to those of the first and second examples depicted inFIG. 5 may be obtained. Further, it was confirmed that in a case of abreakdown voltage structure that similar to the fourth example,satisfies the conditions of both expression (5) and expression (4), theelectric field strength at the surface of the surface protecting film 8could be reduced more than in the third example. From the resultsdepicted in FIGS. 6 and 8, it was confirmed that in the first to fourthexamples, a location (part indicated by reference numeral 42) where theelectric field strength in the silicon carbide base 4 is highest, themaximum electric field strength thereat was substantially equal to thatin the conventional example. In other words, it was found that the firstto fourth examples could sustain the breakdown voltage at the edgetermination region 10 b to a same extent as that in the conventionalexample.

The thickness t2 of the surface protecting film 8 was verified. FIG. 9is characteristics diagram depicting electric field strengthdistribution at the surface of the surface protecting film in a fifthexample. Plural samples (hereinafter, fifth example) having differingthe thicknesses t2 of the surface protecting film 8 were prepared. Thebreakdown voltage structures of the samples in the fifth example weresimilar to that of the third example. Results of measurement of theelectric field strength at the surface of the surface protecting film 8in the samples in the fifth example are depicted in FIG. 9. FIG. 9assumes the thickness t2 of the surface protecting film 8 of one samplein the fifth example as a reference value, and depicts the electricfield strength of the sample taken as the reference and the electricfield strengths at the surface of the surface protecting film 8 in thesamples in which the thickness t2 of the surface protecting film 8 was1.5 times and 2 times that of the sample taking as the reference.

From the results depicted in FIG. 9, it was confirmed that the greaterthe thickness t2 of the surface protecting film 8 is, the greater theelectric field strength at the surface of the surface protecting film 8can be reduced.

As described, according to the embodiment, at least, the length of theelectric field mitigating layer nearest the chip edge (third electricfield mitigating layer) is made longer than the lengths of the otherelectric field mitigating layers, or the length of the space-modulatedregion nearest the chip edge (the third space-modulated region) is madelonger than the lengths of the other space-modulated regions. As aresult, with an edge length substantially equal to that in aconventional structure and with electric field mitigating layers andspace-modulated regions of impurity concentrations substantially equalto those in the conventional structure, a breakdown voltagesubstantially equal to that in the conventional structure may bemaintained while the electric field strength at the surface of thesurface protecting film may be reduced to a greater extent that in theconventional structure. Therefore, in the off state, electricaldischarge occurring at the surface of the surface protecting film due tovoltage application (in the case of a SBD, voltage between the anode andcathode, and in the case of a MOSFET voltage between the drain andsource) may be suppressed. As a result, dielectric breakdown of thesurface protecting film due to electrical discharge, dielectricbreakdown at the gel, and electrostatic breakdown in the silicon carbidebase due to electrical discharge may be prevented, enabling devicereliability to be enhanced.

Further, according to the embodiment, the low-concentration sub-regionsof the space-modulated region nearest the chip edge (the thirdspace-modulated region) are constituted by the n⁻-type silicon carbidelayer (silicon carbide base), whereby variations in the average impurityconcentration of the equal-concentration regions due to ion implantationvariations are smaller than in other space-modulated regions. As aresult, variation of the effect of reducing the electric field at thesurface of the surface protecting film due to increasing the length ofthe space-modulated region nearest the chip edge is small.

Without limitation to the embodiments, various modifications arepossible within a range not departing from the spirit of the inventions.For example, arrangement of the high-concentration sub-regions and thelow-concentration sub-regions of the space-modulated regions may beoptimized so as to reduce the electric field strength in the siliconcarbide base. Further, in the embodiments, while a configuration(arrangement of three electric field mitigating layers and threespace-modulated regions) confirmed to sufficiently ensure the breakdownvoltage in the silicon carbide base and the dielectric breakdown of thesurface protecting film by extensive research of the inventor has beendescribed as an example, provided the space-modulated region nearest thechip edge is arranged, various modifications are possible such aschanging the number of electric field mitigating layers andspace-modulated regions.

In the embodiment, while a case in which a silicon carbide epitaxialsubstrate is used is described as an example, without limitation hereto,similar effects are achieved in a case where without forming anepitaxial growth layer, for example, the regions constituting thebreakdown voltage structure are formed by ion implantation in a surfacelayer on a front surface of a silicon carbide substrate thinly cut froman ingot. Further, the present invention is similarly implemented whenconductivity types (n-type, p-type) are reversed.

According to the embodiment of the silicon carbide semiconductor deviceaccording to the present invention, effects are achieved in that theedge length and the breakdown voltage are maintained while the electricfield strength at the surface of the surface protecting film is reduced.

Thus, the semiconductor device according to the embodiment of thepresent invention is useful for high-voltage silicon carbidesemiconductor devices having a JTE structure and is particularlysuitable for 1200V or higher (for example, 1700V or 3300V) siliconcarbide semiconductor devices.

Although the invention has been described with respect to a specificembodiment for a complete and clear disclosure, the appended claims arenot to be thus limited but are to be construed as embodying allmodifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

What is claimed is:
 1. A silicon carbide semiconductor device,comprising: a semiconductor substrate of a first conductivity typecontaining silicon carbide; an active region provided at a front surfaceof the semiconductor substrate and through which a main current flows; aplurality of second-conductivity-type semiconductor regions selectivelyprovided in a concentric shape surrounding a periphery of the activeregion, the plurality of second-conductivity-type semiconductor regionshaving differing impurity concentrations that are relatively lower withincreasing proximity of respective ones of the plurality ofsecond-conductivity-type semiconductor regions to a chip edge; aplurality of first intermediate regions of a second conductivity type,each first intermediate region of the plurality of first intermediateregions being provided between and in contact with adjacentsecond-conductivity-type semiconductor regions of the plurality ofsecond-conductivity-type semiconductor regions, and each firstintermediate region having an impurity concentration that is lower thanan impurity concentration of an adjacent second-conductivity-typesemiconductor region on an inner side and that is higher than animpurity concentration of another adjacent second-conductivity-typesemiconductor region on an outer side; and a second intermediate regionof the second conductivity type provided closer to the chip edge than isan outermost second-conductivity-type semiconductor region that isnearest the chip edge among the plurality of second-conductivity-typesemiconductor regions, the second intermediate region being in contactwith the outermost second-conductivity-type semiconductor region andhaving an impurity concentration that is lower than the impurityconcentration of the adjacent second-conductivity-type semiconductorregion on an inner side and that is higher than an impurityconcentration of the semiconductor substrate, wherein the plurality offirst intermediate regions and the second intermediate region are eachformed by, from the inner side, a first sub-region of the secondconductivity type and a second sub-region of the second conductivitytype arranged to be adjacent and to alternately repeat in a concentricshape surrounding a periphery of the adjacent second-conductivity-typesemiconductor region on the inner side, the second sub-region having animpurity concentration that is higher than an impurity concentration ofthe first sub-region, and wherein the second intermediate region has alength that is longer than respective lengths of the plurality of firstintermediate regions.
 2. The silicon carbide semiconductor deviceaccording to claim 1, wherein each first intermediate region of theplurality of first intermediate regions has a length that is at leastequal to a length of an adjacent first intermediate region on the innerside thereof.
 3. The silicon carbide semiconductor device according toclaim 1, wherein each second-conductivity-type semiconductor region ofthe plurality of second-conductivity-type semiconductor regions has alength that is longer than a length of the adjacentsecond-conductivity-type semiconductor region on the inner side thereof.4. The silicon carbide semiconductor device according to claim 3,wherein differences in respective lengths of adjacentsecond-conductivity-type semiconductor regions are all equal.
 5. Thesilicon carbide semiconductor device according to claim 1, wherein theimpurity concentration of the first sub-region of respective firstintermediate regions of the plurality of first intermediate regions isequal to the impurity concentration of the respective adjacentsecond-conductivity-type semiconductor region on the outer side.
 6. Thesilicon carbide semiconductor device according to claim 1, wherein theimpurity concentration of the first sub-region of the secondintermediate region is equal to the impurity concentration of thesemiconductor substrate.
 7. The silicon carbide semiconductor deviceaccording to claim 1, wherein the impurity concentration of the secondsub-region is equal to the impurity concentration of the adjacentsecond-conductivity-type semiconductor region on the inner side.
 8. Thesilicon carbide semiconductor device according to claim 1, furthercomprising a surface protecting film provided on the front surface ofthe semiconductor substrate, the surface protecting film covering theplurality of second-conductivity-type semiconductor regions, theplurality of first intermediate regions and the second intermediateregion, wherein the surface protecting film has a thickness that is atleast a maximum thickness that is formable by a single session of anapplication process, based on viscosity of a material used in formingthe surface protecting film.
 9. A silicon carbide semiconductor device,comprising: a semiconductor substrate of a first conductivity typecontaining silicon carbide; an active region provided at a front surfaceof the semiconductor substrate and through which a main current flows; aplurality of second-conductivity-type semiconductor regions selectivelyprovided in a concentric shape surrounding a periphery of the activeregion, the plurality of second-conductivity-type semiconductor regionshaving differing impurity concentrations that are relatively lower withincreasing proximity of respective ones of the plurality ofsecond-conductivity-type semiconductor regions to a chip edge; aplurality of first intermediate regions of a second conductivity type,each first intermediate region of the plurality of first intermediateregions being provided between and in contact with adjacentsecond-conductivity-type semiconductor regions of the plurality ofsecond-conductivity-type semiconductor regions, and each firstintermediate region having an impurity concentration that is lower thanan impurity concentration of an adjacent second-conductivity-typesemiconductor region on an inner side and that is higher than animpurity concentration of another adjacent second-conductivity-typesemiconductor region on an outer side; and a second intermediate regionof the second conductivity type provided closer to the chip edge than isan outermost second-conductivity-type semiconductor region that isnearest the chip edge among the plurality of second-conductivity-typesemiconductor regions, the second intermediate region being in contactwith the outermost second-conductivity-type semiconductor region andhaving an impurity concentration that is lower than the impurityconcentration of the adjacent second-conductivity-type semiconductorregion on an inner side and that is higher than an impurityconcentration of the semiconductor substrate, wherein the plurality offirst intermediate regions and the second intermediate region are eachformed by, from the inner side, a first sub-region of the secondconductivity type and a second sub-region of the second conductivitytype arranged to be adjacent and to alternately repeat in a concentricshape surrounding a periphery of the adjacent second-conductivity-typesemiconductor region on the inner side, the second sub-region having animpurity concentration that is higher than an impurity concentration ofthe first sub-region, and wherein the plurality ofsecond-conductivity-type semiconductor regions each has a length that islonger than a length of the adjacent second-conductivity-typesemiconductor region on the inner side.
 10. The silicon carbidesemiconductor device according to claim 9, further comprising a surfaceprotecting film provided on a front surface of the semiconductorsubstrate, the surface protecting film covering the plurality ofsecond-conductivity-type semiconductor regions, the plurality of firstintermediate regions and the second intermediate region, wherein thesurface protecting film has a thickness that is at least a maximumthickness that is formable by a single session of an applicationprocess, based on viscosity of a material used in forming the surfaceprotecting film.